/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */


`include "defines.v"

// Hold_None 3'b000     == stall {6'b000000}
// Hold_Pc   3'b001	== stall {6'b000001}
// Hold_If   3'b010     == stall {6'b000011}
// Hold_Id   3'b011     == stall {6'b000111}


module ctrl(
	input wire	rst,

	// from ex
	input wire	branch_flag_i,
	input wire[`RegBus]	branch_target_address_i,
	input wire	stallreq_from_id,
	input wire	stallreq_from_ex,
	output reg[`StallBus] stall,
	// to pc reg
	output reg	branch_flag_o,
	output reg	flush_inst_o,
	output reg[`RegBus]	branch_target_address_o
);

	always @ (*) begin
		branch_flag_o <= branch_flag_i;
		branch_target_address_o <= branch_target_address_i;
		if (rst == `RstEnable) begin
			stall <= 6'b000000;
			flush_inst_o <= 1'b0;
		end else if (branch_flag_i == `Branch) begin
			stall <= 6'b000000;
			flush_inst_o <= 1'b1;
		end else if (stallreq_from_ex == `Stop) begin
			stall <= 6'b001111;
			flush_inst_o <= 1'b0;
		end else if (stallreq_from_id == `Stop) begin
			stall <= 6'b000111;
			flush_inst_o <= 1'b0;
		end else begin
			stall <= 6'b000000;
			flush_inst_o <= 1'b0;
		end
	end

endmodule
